The present invention is directed, in general, to processing systems and, more specifically, to a data processor coupled to one or more peripheral devices via a Peripheral Component Interconnect (PCI) bus.
In order to extend the capabilities of data processing systems, particularly PCs, many microprocessor-based architectures implement a Peripheral Component Interconnect (PCI) bus that allows peripheral devices to be added to the system. Because of its relative ease of use and flexibility, the PCI bus has become one of the most popular electronic standards in history. The PCI bus forms the main general-purpose bus in nearly all PCs worldwide. For example, Microsoft(copyright) Windows(copyright) 32-bit operating systems use the PCI bus to gather data about peripheral devices attached to the PCI bus. This is particularly important with respect to the Plug and Play features of Windows(copyright).
In addition to the conventional main memory and input/output (I/O) address spaces used by conventional microprocessors, every PCI device in a processing system, including PCI bridges, has a configuration data table somewhere in the PCI configuration address space. The PCI configuration header allows the processing system to identify and control the PCI device. The location of the PCI configuration header in the PCI configuration address space depends on the location of the PCI device on the PCI bus. For example, a PCI video card plugged into one PCI slot will have its configuration header in one location. If the PCI video card is plugged into another PCI slot, its configuration header will appear in another location in PCI configuration address space.
Configuration address space is a physical address unique to the PCI bus. Configuration cycles are generated in the microprocessor. The configuration registers of each PCI device are accessed through the PCI interface. The PCI interface uses two I/O locations at addresses 0CF8(hex) and 0CFC(hex). The 0CF8h address references the Configuration Address register. The 0CFCh address references the Configuration Data register. To access PCI configuration space, a data value is written to the Configuration Address register that specifies the PCI bus, the PCI device on that bus, the function number of the PCI device, and the configuration register in the PCI device that is being accessed. A subsequent read or write to the Configuration Data register causes the PCI bridge to translate the data value in the Configuration Address register in order to access the configuration register and the configuration memory for the PCI device. A configuration memory of 256 bytes is provided for each PCI device.
Motherboard devices, such as graphics or audio, may not implement configuration space in hardware in order to simplify the hardware design. Alternatively, a hardware implementation may not provide full functionality. Microsoft(copyright) Plug and Play features and WINDOWS 98(copyright) (operating system) multiple monitor capabilities require the use of PCI configuration space. The hardware for the PCI configuration space must be present even if, for example, multiple monitors are not used in the processing system.
Furthermore, some multifunction or programmable devices can be configured to represent any number of PCI device types. For example, a digital signal processor (DSP) board may be configured as an audio device, a video device, a modem, a data capture device, test equipment, or as some other function. Design flexibility is lost since the configuration space for the DSP board is implemented in hardware on the motherboard in the final product and cannot be changed.
Therefore, there is a need in the art for improved processing system architectures in which PCI bus requirements are more flexible. In particular, there is a need for improved processing systems that minimize the amount of hardware required to serve one or more PCI devices coupled to the PCI bus of the processing system. More particularly, there is a need for an improved processing system architecture in which operating system accesses to PCI devices that are not present on the PCI bus may be handled without utilizing special purpose configuration space hardware.
The limitations inherent in the prior art described above are overcome in the present invention which provides an apparatus for providing a virtual PCI device for use in a processing system comprising a data processor having an external peripheral bus coupled thereto in which peripheral devices associated with the external bus are controlled by accessing configuration circuitry associated with each of the peripheral devices. In an advantageous embodiment of the present invention, the apparatus for providing a virtual PCI device comprises: a) an address trap circuit capable of detecting a configuration cycle capable of accessing a virtual configuration address space associated with the virtual PCI device and, in response to the detection, generating an enable signal; and b) an interrupt generation circuit associated with the address trap circuit capable of receiving the enable signal, and in response thereto, generating an interrupt signal capable of causing the data processor to execute a plurality of instructions associated with the virtual device.
According to one embodiment of the present invention, the apparatus further comprises a memory associated with data processor capable of storing the plurality of instructions.
According to another embodiment of the present invention, the external bus comprises a Peripheral Component Interconnect (PCI) bus.
According to still another embodiment of the present invention, the address trap circuit and the interrupt generation circuit are disposed in a PCI bridge associated with the data processor.
According to yet another embodiment of the present invention, the PCI bridge is external to the data processor.
According to a further embodiment of the present invention, the PCI bridge is integrated into the data processor.
According to a still further embodiment of the present invention, at least one of the address trap circuit and the interrupt generation circuit is programmable, such that the interrupt signal is generated only for selected ones of bus numbers, and/or function numbers, and/or device numbers associated with the external bus.
According to a yet further embodiment of the present invention, the plurality of instructions are stored in system management mode address space in a memory associated with the data processor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.